iadc
Project Library Model Name Kind
ISCD_IADC adc_top iadc Hierarchical Module

Parameters

Name Type Default Description
c double 10e-12 integrator capacitor [F]
r double 2e6 integrator resistor [Ohm]
intgain double 250 integrator gain [V/V]
compbw double 1e5 comparator bandwidth [Hz]

Ports

Name Interface Type Description
clk50m_i sc_core::sc_in bool ADC clock, usually 50MHz
resn_i sc_core::sc_in bool ADC reset and halt (low-active)
adc_o sc_core::sc_out int ADC result (valid when eoc_o is high)
eoc_o sc_core::sc_out bool ADC end of conversion
vin_p sca_eln::sca_terminal ADC differential input "plus"
vin_n sca_eln::sca_terminal ADC differential input "minus"
vref_p sca_eln::sca_terminal ADC reference input "plus"
vref_n sca_eln::sca_terminal ADC reference input "minus"
vsup sca_eln::sca_terminal ADC supply

Description

hierarchic symbol

Schematic

vdd inp inn vss outn vcm outp diffamp_cm gain = p.intgain r_div = 1e3 fc = 100e6 offset = 1e-3 + - - + d1 c o1 o1q comp_ff <bool > delay = 0.5_SC_PS ! gnd p n c_n value = p.c p n c_p value = p.c p n r_p value = p.r p n r_n value = p.r p n int_res_p ron = 1e3 roff = 1e8 false p n int_res_n ron = 1e3 roff = 1e8 false p n in_p ron = 1e2 roff = 1e8 false p n in_n ron = 1e2 roff = 1e8 false p n ref_a_p ron = 1e2 roff = 1e8 false p n ref_a_n ron = 1e2 roff = 1e8 false p n ref_b_p ron = 1e2 roff = 1e8 false p n ref_b_n ron = 1e2 roff = 1e8 false integrating ADC Carinthia University of Applied Science Author: W. Scherr, Date: JAN 2021 vin_p vin_n vref_p vref_n c = 10e-12 r = 2e6 intgain = 250 adc_o OUT BOUNDARY Analog | Digital scrollfixer comp_i resn_comp_o adc_o eoc_o dig_control IADC_CONTROL eoc_o OUT scrollfixer outn inp inn diffcomp_single gain = 1.0e3 fc = p.compbw offset = 2e-3 + - compbw = 1e5 vint_n vint_p vcm comp comp_sync comp_sync_n resn_comp clk50m_i n2 n1 S3 int_in_p int_in_n S1 S2a S2b