Project	Library	Model Name	Kind
ISCD_IADC	digital_blocks	iadc_control	SystemC Module

Ports

Name	Interface	Type	Description
clk_i	sc_core::sc_in	bool	system clock, usually 50MHz
resn_i	sc_core::sc_in	bool	reset/hold input (synchronous)
comp_i	sc_core::sc_in	bool	comparator input, must be synchronised
resn_comp_o	sc_core::sc_out	bool	comparator reset output
S1_o	sc_core::sc_out	bool	set input to integrator input
S2a_o	sc_core::sc_out	bool	set reference directly to integrator input
S2b_o	sc_core::sc_out	bool	set reference crossed out to integrator input
S3_o	sc_core::sc_out	bool	reset integrator (dicharge caps)
adc_o	sc_core::sc_out	int	adc result output (only valid when eoc_o is high)
eoc_o	sc_core::sc_out	bool	end of conversion output

Description

IADC control logic

See here for the CPP code containing the behavior as simple sequence of "clock-cycle actions" of the control part.