| Project | Library | Model Name | Kind |
| ISCD_IADC | analog_blocks | diff_comp_sc | Hierarchical Module |
Parameters
| Name | Type | Default | Description |
| gain | double | 1.0 | DC gain [V/V] |
| fc | double | 1e6 | corner frequency [Hz] |
| offset | double | 0.001 | input offset [V] |
Ports
| Name | Interface | Type | Description |
| outn | sc_core::sc_out | bool | comparator output (inverted) |
| inp | sca_eln::sca_terminal | differential input ("plus") | |
| inn | sca_eln::sca_terminal | differential input ("minus") |
Description
differential comparator
Long Description
Differential comparator with limited bandwidth (1.O. butterworth).Schematic