Parameters
| Name | Type | Default | Description |
| delay | sc_core::sc_time | 0.5_SC_PS | gate delay from any input to output [sc_time] |
Ports
| Name | Interface | Type | Description |
| d1 | sc_core::sc_in | T | data input 1 |
| c | sc_core::sc_in | T | clock input (rising edge) |
| rn | sc_core::sc_in | T | async. low-act. reset input (higher prio) |
| o1 | sc_core::sc_out | T | logic output 1 |
| o1q | sc_core::sc_out | T | logic output 1 (inverted) |
Description
FF with async. reset