Name	Description
and2_de	AND gate, 2 inputs, 1 output
buf_de	buffer gate, 1 input, 1 output
dff_de	FF with async. reset
inv_de	inverter gate, 1 input, 1 output
nand2_de	NAND gate, 2 inputs, 1 output
nor2_de	(inclusive) NOR gate, 2 inputs, 1 output
or2_de	(inclusive) OR gate, 2 inputs, 1 output
rsff_de	set/reset FF (reset has prio)
xnor2_de	exclusive NOR gate, 2 inputs, 1 output
xor2_de	exclusive OR gate, 2 inputs, 1 output