and2_de
Project Library Model Name Kind
ISCD_IADC logic and2_de SystemC Module

Parameters

Name Type Default Description
delay sc_core::sc_time 1.0_SC_PS gate delay from any input to output [sc_time]

Ports

Name Interface Type Description
i1 sc_core::sc_in T logic input 1
i2 sc_core::sc_in T logic input 2
o1 sc_core::sc_out T logic output 1

Description

AND gate, 2 inputs, 1 output