all_gates
Project Library Model Name Kind
ISCD_IADC logic_test all_gates Hierarchical Module

Description

hierarchic symbol

Long Description

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Schematic

<enter text> Simple TB for all digital gates; run for at least 5ns. (c) CUAS W. Scherr i1 i2 o1 i_and2_de1 <bool > delay = 100.0_SC_PS clk_o i_clock_src_sc1 <bool> high_level = {T}(1) low_level = {T}(0) period = 1.0_SC_NS start_time = sc_core::SC_ZERO_TIME duty_cycle = 0.5 CLOCK_SRC_SC t high_level low_level clk_o i_clock_src_sc2 <bool> high_level = {T}(1) low_level = {T}(0) period = 2.0_SC_NS start_time = sc_core::SC_ZERO_TIME duty_cycle = 0.5 CLOCK_SRC_SC t high_level low_level i1 i2 o1 i_or2_de1 <bool > delay = 100.0_SC_PS i1 i2 o1 i_xor2_de1 <bool > delay = 300.0_SC_PS i1 i2 o1 i_nor2_de1 <bool > delay = 70.0_SC_PS i1 i2 o1 i_nand2_de1 <bool > delay = 70.0_SC_PS i1 i2 o1 i_xnor2_de1 <bool > delay = 250.0_SC_PS i1 o1 i_buf_de1 <bool > delay = 80.0_SC_PS i1 o1 i_inv_de1 <bool > delay = 50.0_SC_PS s1 r1 o1 o1q i_rsff_de1 <bool > delay = 100.0_SC_PS ! d1 c o1 o1q i_dff_de1 <bool > delay = 50.0_SC_PS ! clk_o i_clock_src_sc3 <bool> high_level = {T}(0) low_level = {T}(1) period = 0.5_SC_NS start_time = sc_core::SC_ZERO_TIME duty_cycle = 0.5 CLOCK_SRC_SC t high_level low_level inputs_1 inputs_2 and_output or_output xor_output nand_output nor_output xnor_output buf_output inv_output rsff_output rsff_output_q dff_output dff_output_q inputs_3